Content addressable memory (CAM) devices enjoy wide applications due to their ability to provide rapid match results between an applied compare data value (a comparand) and numerous stored data values.
A continuing goal for integrated circuits is that of lower power consumption and/or reduced peak current consumption. In the particular case of CAM devices, compare operations can consume considerable current (and hence power), as such operations typically involve the continuous charging of multiple match lines and/or compare data lines, and the subsequent discharging of such lines.
To better understand such concerns, a compare operation for a conventional CAM device will now be described.
Referring to FIG. 9, a conventional compare (e.g., sensing) operation is set forth in a timing diagram. FIG. 9 shows the potentials of 128 match lines ML0 to ML127. In a precharge portion of a compare operation, the match lines (ML0 to ML127) can be precharged to a high potential (VCC). The potential of each match line (ML0 to ML127) can represent the comparison between a comparand value and a data value corresponding to the match line. In a subsequent sensing portion of the compare operation, an applied comparand value can be compared to the stored data values. If a stored data value does not match the comparand value (i.e., a mismatch or MISS condition), the corresponding match line is discharged to a low potential (VSS). In contrast, if a stored data value matches the comparand value (i.e., a match or HIT condition), the corresponding match line remains unchanged at the high potential (VDD).
Referring still to FIG. 9, match lines ML0, ML1 and ML127 indicate a MISS by being discharged at time t0, while match line MLn indicates a HIT by remaining charged at this time.
Following the sensing portion, in a subsequent precharge portion, the match lines (ML0 to ML127) may be precharged once more, so that all lines are returned to a high potential (e.g., VCC or VCC-Vtn).
In a normal operating mode, very few (ideally one) match lines will indicate a HIT and not be discharged, while the majority of match lines will indicate a miss and be discharged. Such discharged match lines will require subsequent precharging to accomplish a next compare operation. Thus, as compare operations are undertaken, the majority of match lines are continuously charged and then discharged, consuming relatively large amounts of power.
Similarly, in a conventional CAM device, a comparand value is typically a multiple bit value. Each bit can be applied by complementary signal lines. Such signal lines can carry complementary logic signals in a compare operation. Alternatively, such signal lines may carry a same logic value in the event a “global” bit masking is implemented. That is, if a comparand value consisted of 16 bits CD0 to CD15, within a CAM device, such bit values could be applied as complementary comparand signals CD0/BCD0, CD1/BCD1 . . . CD15/BCD15. As comparand values change for each different compare operation, such comparand lines can be driven to different values. The charging and discharging of lines carrying such complementary comparand bit values can also consume current.
One approach to conserving power in relation to compare data lines is shown in U.S. Pat. No. 6,504,740, titled CONTENT ADDRESSABLE MEMORY HAVING COMPARE DATA TRANSITION DETECTOR issued to Eric H. Voelkel on Jan. 7, 2003 (hereinafter Voelkel). Voelkel discloses an arrangement in which transitions in compare data lines can be avoided for those bits that do not change between subsequent comparand values.
One example of a sense amplifier that can be used in a CAM device is shown in U.S. patent application Ser. No. 10/873,608, filed Jun. 22, 2004, titled SENSE AMPLIFIER CIRCUIT FOR CONTENT ADDRESSABLE MEMORY DEVICE by Anita X. Meng et al. (hereinafter Meng et al.) The contents of this application are included herein with this patent application. Meng et al. discloses an arrangement in which a charge can be conserved by equalizing the potential of a match line with a “pseudo” supply line.
A conventional sense amplifier circuit is disclosed in “A Ternary Content-Addressable Memory (TCAM) Based on 4T Static Storage and Including Current-Race Sensing Scheme”, IEEE Journal of Solid-State Circuits, Vol. 38, No. 1, January 2003, pp. 155–158 by Arsovski et al Another conventional sense amplifier circuit is shown in “A Current-Saving Match-Line Sensing Scheme for Content-Addressable Memories”, ISSCC 2003, Session 17, SRAM and DRAM, Paper 17.3 by Arsovskl at al., pp. 304–305.
Yet another conventional sense amplifier is shown in FIG. 10. FIG. 10 shows an example of a single ended sense amplifier employed in a ternary CAM device. In FIG. 10, a sense amplifier 1000 can be coupled to a compare stack 1002. A compare stack 1002 represents one of many bit compares in a sense operation. Such bit compares can compare a compare data value (represented by complementary values CD and BCD) to a data value (represented by complementary values D and BD). A compare result is maskable by a mask value mask. Such a masking capability can form a “ternary” CAM device, as opposed to a binary CAM device.
The conventional sense amplifier 1000 includes p-channel precharge transistors P101 and P102 having sources commonly connected to a power supply voltage VCC, and gates commonly connected to a precharge signal prechg. The conventional sense amplifier 1000 also includes a holding n-channel transistor N 01 and sensing n-channel transistor N102. Transistors N101 and N102 may have drains connected to the drains of transistors P101 and P102, respectively. The sources of transistors N101 and N102 can be commonly connected to a match line match. The gates of transistors N101 and N102 can be commonly connected to a voltage VCCQ. A voltage VCCQ can maintain transistors N101 and N102 in an off state when a match line match is precharged, as will be described below.
The drain—drain connection of transistors P102 and N102 can be connected to a sense node msaint. Sense node msaint can be precharged by precharge p-channel transistor P102 arranged in series between node msaint and power supply voltage VCC. The potential at sense node msaint can be buffered by series connected inverters INV101 and INV102 to provide sense amplifier output signal saout. Transistors P103 and P104 can be optional negative feedback control devices. Transistors P103 and P104 can act as weak “keeper” devices to help maintaining node msaint at a VCC potential.
The operation of the conventional sense amplifier 1000 will now be described.
In a pre-sense period, match line match can be precharged to a voltage VCC-Vtn1. A value Vtn1 can be the threshold voltage of holding transistor N101. It is noted that sensing transistor N102 is designed to have a higher threshold voltage (e.g., at least 200 mV) than holding transistor N101. Thus, once match line match is precharged to VCC-Vtn1, sensing transistor N102 is turned off.
In a sense period, data values can be compared within a compare stack 1002. In the event a sense operation indicates a match (e.g., a HIT), all compare stacks 1002 can maintain a relatively high impedance between the match line match and ground (VSS). In this state, the sense amplifier 1000 can utilize the difference in threshold voltages of transistors N101 and N102, to keep transistor N102 turned off. With transistor N102 turned off, sense node msaint can be maintained at the precharged VCC potential. Consequently, sense amplifier output signal saout remains high, indicating a HIT state. As noted above, it can be optional to connect a weak keeper device as shown in FIG. 10. This can prevent the node msaint voltage from leaking to a lower voltage.
In the event a sense operation indicates a mis-match (e.g., a MISS), at least one compare stacks 1002 will provide a relatively low impedance between the match line match and ground (VSS). Thus, the match line match will go toward ground (VSS). When the gate-to-source voltage of transistor N102 is larger than Vtn2, the sense transistor N102 will turn on. With transistor N102 on, sense node msaint will discharge through sense transistor N102 and the compare stack 1002 to ground (VSS). Consequently, the sense amplifier output signal saout transitions low, indicating a MISS state.
Thus, the conventional sense amplifier 1000 operation can include precharging a match line match to VCC-Vtn1, and then discharging the same match line match in the event of a MISS state. It is understood that a conventional CAM includes numerous match lines, and in operation, MISS states are typically far more common than HIT states. As a result, such match operations can consume considerable current as match lines are continuously precharged and then discharged.
One example of a CAM device that can reduce current consumption is shown in U.S. Pat. No. 6,515,884, titled CONTENT ADDRESSABLE MEMORY HAVING REDUCED CURRENT CONSUMPTION, issued to Stefan P. Sywyk et al., on Feb. 4, 2003 (Sywyk et al.). Sywyk et al. shows a various particular examples of a CAM device that can include a “pseudo-VSS” arrangement that can conserve power by regulating match line discharge paths.
As noted above, it is always desirable to arrive at some way of reducing power consumption and/or peak current in CAM devices. However, such gains should not adversely affect performance, such as by reducing operation speed.